Digital circuits may include multiple clock domains having different frequencies. When the signals cross from one clock domain to another clock domain, the signals need to be synchronized. If the signals are not synchronized, signal values may be indeterminate when sampled by the other clock domain due to metastability.
FIG. 1 depicts a conventional circuit for synchronizing signals from one clock domain to another clock domain. As shown at FIG. 1, two D-type flip-flops (“double register”) are each clocked by the receiving clock domain. The synchronizer shown at FIG. 1, however, is limited to synchronizing signals where the clock frequencies of the sending and receiving clock domains are approximately the same or when the sending clock domain is slower than the receiving clock domain.
FIG. 2 depicts a timing diagram illustrating the results of signals sent and received using the conventional circuit of FIG. 1 when the sending clock domain is faster (i.e. on the order of 2× or more) than the receiving clock domain. As shown at FIG. 2, both the sending and receiving logic use the rising edges of their clocks to generate and sample the signal crossing from one clock domain to the other.
When the sending clock domain is faster than the receiving clock domain, signals of short duration that are sent by the faster sending clock domain may be missed entirely by the slower receiving clock domain, resulting in an unreliable transfer of data or control signals from the fast clock domain to the slower clock domain. Further, the simple synchronizer in FIG. 1 does not provide means for the sending logic to determine when it is safe to generate a new signal to be sent to the receiving logic. Accordingly, there is a need for more efficient and accurate synchronizing logic.